AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 248

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Table 41. L1 and L2 Cache States for Snoops, Flushes, and Invalidation
Notes:
1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache
2. Writeback cycles to the bus are 32-byte burst writes.
3. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in
— Not applicable or none.
226
Operation Type
Internal Snoop
FLUSH# Signal
PFIR (F/I = 0)
PFIR (F/I = 1)
WBINVD Instruction
INVD Instruction
and are treated as “valid” states.
the modified state in the L2 cache.
Cache State Before Operation
L1
E
M
M
M
M
M
–
E
E
S
S
–
–
–
–
I
I
I
I
3
Table 41 shows all possible cache-line states before and after
various cache-related operations.
S or E
S or E
S or E
Preliminary Information
M
L2
M
M
M
M
Cache Organization
–
–
–
–
–
E
S
E
E
S
I
I
I
I
3
1
Access Type
–
–
–
–
–
–
–
Writeback L1 to L2
Writeback L1 to bus
–
–
–
Writeback L1 to bus
Writeback L2 to bus
–
Writeback L1 to bus
Writeback L2 to bus
–
–
Writeback L1 to bus
Writeback L2 to bus
–
2
Cache State After Operation
L1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
23543A/0—September 2000
Chapter 9
L2
M
M
M
E
S
E
S
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I