AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 149

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
5.40
Pin Attribute
Summary
Sampled
Chapter 5
RESET (Reset)
Input
When the processor samples RESET asserted, it immediately
flushes and initializes all internal resources and its internal
state including its pipelines and caches, the floating-point
state, the MMX state, the 3DNow! state, and all registers, and
then the processor jumps to address FFFF_FFF0h to start
instruction execution.
The FLUSH# signal is sampled during the falling transition of
RESET to invoke the Three-State Test mode.
RESET is sampled as a level-sensitive input on every clock
edge. System logic can drive the signal either synchronously or
asynchronously.
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and V
reach specification before it is negated.
During a warm reset, while CLK and V
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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are within their
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