AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 271
AMD-K6-IIIE+550ACR
Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AMD-K6-IIIE550ACR.pdf
(370 pages)
Specifications of AMD-K6-IIIE+550ACR
Lead Free Status / RoHS Status
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23543A/0—September 2000
Chapter 12
Table 49 shows the format of the I/O trap restart slot.
Table 49. I/O Trap Restart Slot
The processor initializes the I/O trap restart slot to 0000h upon
entry into SMM. If SMM was entered due to a trapped I/O
instruction, the processor indicates the validity of the I/O
instruction by setting or clearing bit 1 of the I/O trap
doubleword at offset FFA4h in the SMM state-save area. The
S MM se rvice ro u tine should t es t b it 1 of the I/ O t ra p
doubleword to determine if a valid I/O instruction was being
executed when entering SMM and before writing the I/O trap
restart slot. If the I/O instruction is valid, the SMM service
routine can safely rewrite the I/O trap restart slot with the value
00FFh, which causes the processor to re-execute the trapped I/O
instruction when the RSM instruction is executed. If the I/O
instruction is invalid, writing the I/O trap restart slot has
undefined results.
If a second SMI# is asserted and a valid I/O instruction was
trapped by the first SMM handler, the processor services the
second SMI# prior to re-executing the trapped I/O instruction.
The second entry into SMM never has bit 1 of the I/O trap
doubleword set, and the second SMM service routine must not
rewrite the I/O trap restart slot.
During a simultaneous SMI# I/O instruction trap and debug
breakpoint trap, the AMD-K6-IIIE+ processor first responds to
the SMI# and postpones recognizing the debug exception until
after returning from SMM via the RSM instruction. If the debug
registers DR3–DR0 are used while in SMM, they must be saved
and restored by the SMM handler. The processor automatically
saves and restores DR7–DR6. If the I/O trap restart slot in the
SMM state-save area contains the value 00FFh when the RSM
instruction is executed, the debug trap does not occur until
after the I/O instruction is re-executed.
31–16
Reserved
System Management Mode (SMM)
15–0
I/O Instruction restart on return from SMM:
0000h = execute the next instruction after the trapped I/O
00FFh = re-execute the trapped I/O instruction
AMD-K6™-IIIE+ Embedded Processor Data Sheet
249
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