AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 265

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
12.2
Chapter 12
SMM State-Save Area
Table 45 shows the initial state of registers when entering SMM.
Table 45. Initial State of Registers in SMM
When the processor acknowledges an SMI# interrupt by
asserting SMIACT#, it saves its state in a 512-byte SMM
state-save area shown in Table 46. The save begins at the top of
the SMM memory area (SMM base address + FFFFh) and fills
down to SMM base address + FE00h.
Table 46 shows the offsets in the SMM state-save area relative
to the SMM base address. The SMM service routine can alter
any of the read/write values in the state-save area.
Table 46. SMM State-Save Area Map
Registers
General Purpose Registers
EFLAGS
CR0
DR7
GDTR, LDTR, IDTR, TSSR, DR6
EIP
CS
DS, ES, FS, GS, SS
System Management Mode (SMM)
Address Offset
FFDCh
FFD8h
FFD4h
FFD0h
FFFCh
FFECh
FFF8h
FFF4h
FFF0h
FFE8h
FFE4h
FFE0h
AMD-K6™-IIIE+ Embedded Processor Data Sheet
SMM Initial State
unmodified
0000_0002h
PE, EM, TS, and PG are cleared (bits 0, 2, 3, and
31). The other bits are unmodified.
0000_0400h
unmodified
0000_8000h
0003_0000h
0000_0000h
Contents Saved
EFLAGS
EDX
CR0
CR3
EBP
EBX
ECX
EAX
ESP
EIP
EDI
ESI
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