AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 145

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
5.36
Pin Attribute
Summary
Sampled
Chapter 5
NMI (Non-Maskable Interrupt)
Input
When NMI is sampled asserted, the processor jumps to the
interrupt service routine defined by interrupt number 02h.
Unlike the INTR signal, software cannot mask the effect of NMI
if it is sampled asserted by the processor. However, NMI is
temporarily masked upon entering System Management Mode
(SMM). In addition, an interrupt acknowledge cycle is not
executed because the interrupt number is predefined.
If NMI is sampled asserted while the processor is executing the
interrupt service routine for a previous NMI, the subsequent
NMI remains pending until the completion of the execution of
the IRET instruction at the end of the interrupt service routine.
NMI is sampled and latched as a rising edge-sensitive signal.
During normal operation, NMI is sampled on every clock edge
but is not recognized until the next instruction boundary.
If NMI is asserted synchronously (see Table 19 on page 140),
it can be asserted for a minimum of one clock.
If NMI is asserted asynchronously, it must have been
negated for a minimum of two clocks, followed by an
assertion of a minimum of two clocks.
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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