AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 272

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
12.8
250
Exceptions, Interrupts, and Debug in SMM
During an SMI# I/O trap, the exception/interrupt priority of the
AMD-K6-IIIE+ processor changes from its normal priority. The
normal priority places the debug traps at a priority higher than
the sampling of the FLUSH# or SMI# signals. However, during
an SMI# I/O trap, the sampling of the FLUSH# or SMI# signals
takes precedence over debug traps.
The processor recognizes the assertion of NMI within SMM
immediately after the completion of an IRET instruction. Once
NMI is recognized within SMM, NMI recognition remains
enabled until SMM is exited, at which point NMI masking is
restored to the state it was in before entering SMM.
System Management Mode (SMM)
Preliminary Information
23543A/0—September 2000
Chapter 12