AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 190

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
7.5
Hold and Hold
Acknowledge Cycle
168
Inquire and Bus Arbitration Cycles
The AMD-K6-IIIE+ processor provides built-in level-one (L1)
data and instruction caches, and a unified level-two (L2) cache.
Each L1 cache is 32 Kbytes and two-way set-associative. The L2
cache is 256 Kbytes and four-way set-associative. The system
logic or other bus master devices can initiate an inquire cycle to
maintain cache/memory coherency. In response to the inquire
cycle, the processor compares the inquire address with its cache
tag addresses in all caches, and, if necessary, updates the MESI
state of the cache line and performs writebacks to memory.
An inquire cycle can be initiated by asserting AHOLD, BOFF#,
or HOLD. AHOLD is exclusively used to support inquire cycles.
During AHOLD-initiated inquire cycles, the processor only
floats the address bus. BOFF# provides the fastest access to the
bus because it aborts any processor cycle that is in-progress,
whereas AHOLD and HOLD both permit an in-progress bus
cycle to complete. During HOLD-initiated and BOFF#-initiated
inquire cycles, the processor floats all of its bus-driving signals.
The AMD-K6-IIIE+ processor does not support system-initiated
inquire cycles during the Enhanced Power Management (EPM)
Stop Grant State. For more information on the EPM Stop Grant
State, see “Clock Control” on page 277.
The system logic or another bus device can assert HOLD to
initiate an inquire cycle or to gain full control of the bus. When
the AMD-K6-IIIE+ processor samples HOLD asserted, it
completes any in-progress bus cycle and asserts HLDA to
acknowledge release of the bus. The processor floats the
following signals off the same clock edge on which HLDA is
asserted:
A[31:3]
ADS#
AP#
BE[7:0]#
CACHE#
D[63:0]
D/C#
Preliminary Information
Bus Cycles
DP[7:0]
LOCK#
M/IO#
PCD
PWT
SCYC
W/R#
23543A/0—September 2000
Chapter 7