AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 269

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
12.6
Chapter 12
I/O Trap Doubleword
Upon entry into SMM, the halt restart slot is defined as follows:
After entry into the SMI handler and before returning from
SMM, the halt restart slot can be written using the following
definition:
If the return from SMM takes the processor back to the Halt
state, the HLT instruction is not re-executed, but the Halt
special bus cycle is driven on the bus after the return.
If the assertion of SMI# is recognized during the execution of an
I/O instruction, the I/O trap doubleword at offset FFA4h in the
S M M s t a t e -s ave a re a c o n t a i n s i n fo r m a t i o n ab o ut t h e
instruction. The fields of the I/O trap doubleword are
configured as follows:
Bits 15–1—Reserved
Bit 0—Point of entry to SMM:
1 = entered from Halt state
0 = not entered from Halt state
Bits 15–1—Reserved
Bit 0—Point of return when exiting from SMM:
1 = return to Halt state
0 = return to next instruction after the HLT instruction
Bits 31–16—I/O port address
Bits 15–4—Reserved
Bit 3—REP (repeat) string operation
(1 = REP string, 0 = not a REP string)
Bit 2—I/O string operation
(1 = I/O string, 0 = not an I/O string)
Bit 1—Valid I/O instruction (1 = valid, 0 = invalid)
Bit 0—Input or output instruction (1 = INx, 0 = OUTx)
System Management Mode (SMM)
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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