AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 259

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
11
11.1
Handling
Floating-Point
Exceptions
Chapter 11
Floating-Point and Multimedia Execution Units
Floating-Point Execution Unit
The AMD-K6-IIIE+ processor contains an IEEE 754-compatible
and 854-compatible floating-point execution unit designed to
accelerate the performance of software that utilizes the x86
floating-point instruction set.
Floating-point software is typically written to manipulate
numbers that are very large or very small, that require a high
degree of precision, or that result from complex mathematical
operations such as transcendentals. Applications that take
advantage of floating-point operations include geometric
calculations for graphics acceleration, scientific, statistical, and
engineering applications, and business applications that use
large amounts of high-precision data.
The high-performance floating-point execution unit contains an
adder unit, a multiplier unit, and a divide/square root unit.
These low-latency units can execute floating-point instructions
in as few as two processor clocks. To increase performance, the
proce sso r is de sig ned to simul ta neo usly de code mo st
floating-point instructions with most short-decodeable
instructions.
See “Software Environment” on page 27 for a description of the
floating-point data types, registers, and instructions.
The AMD-K6-IIIE+ processor provides the following two types
of exception handling for floating-point exceptions:
Floating-Point and Multimedia Execution Units
If the numeric error (NE) bit in CR0 is set to 1, the processor
invokes the interrupt 10h handler. In this manner, the
floating-point exception is completely handled by software.
If the NE bit in CR0 is set to 0, the processor requires
external logic to generate an interrupt on the INTR signal in
order to handle the exception.
AMD-K6™-IIIE+ Embedded Processor Data Sheet
237