AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 242

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
9.9
Hardware
Prefetching
Software Prefetching
220
Prefetching
9. Between 15–16 Mbytes—If the address of a pending write
10. Write Allocate Enable 15–16 Mbytes (WAE15M)—This
The AMD-K6-IIIE+ processor conditionally performs cache
prefetching, which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
burst read cycles occurring back-to-back or, if allowed, as
p i p e l in e d cy c le s . The b u rst re a d cy c l e s d o n o t o c c u r
back-to-back (wait states occur) if the processor is not ready to
start a new cycle, if higher priority data read or write requests
exist, or if NA# (next address) was sampled negated. Wait states
can also exist between burst cycles if the processor samples
AHOLD or BOFF# asserted.
The 3DNow! technology includes an instruction called
PREFETCH that allows a cache line to be prefetched into the
L1 data cache and the L2 cache. Unlike prefetching under
hardware control, software prefetching only fetches the cache
line specified by the operand of the PREFETCH instruction,
and does not attempt to fetch the other cache line in the sector.
The PREFETCH instruction format is defined in Table 15,
“3DNow!™ Instructions,” on page 89. For more detailed
information, see the 3DNow!™ Technology Manual, order#
21928.
cycle is in the 1 Mbyte of memory between 15 Mbytes and
16 Mbytes, and the WAE15M bit is set to 1, write allocate
for this cycle is enabled.
condition is associated with the Write Allocate Limit
mechanism and affects write allocate only if the limit
specified by the WAELIM field is greater than or equal to
16 Mbytes. If the memory address is between 15 Mbytes and
16 Mbytes, and the WAE15M bit in the WHCR is set to 0,
write allocate for this cycle is disabled (even if condition 10
attempts to prevent write allocate, condition 5 or 6 allows
write allocate to occur).
Preliminary Information
Cache Organization
23543A/0—September 2000
Chapter 9