AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 118

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.4
Pin Attribute
Summary
Driven and Floated
5.5
Pin Attribute
Summary
96
ADS# (Address Strobe)
ADSC# (Address Strobe Copy)
Output
The assertion of ADS # indicates the beginning of a new bus
cycle. The address bus and all cycle definition signals
corresponding to this bus cycle are driven valid off the same
clock edge as ADS#.
ADS # is asserted for one clock at the beginning of each bus
cycle. For non-pipelined cycles, ADS# can be asserted as early
as the clock edge after the clock edge on which the last
expected BRDY# of the cycle is sampled asserted, resulting in a
single idle state between cycles. For pipelined cycles if the
processor is prepared to start a new cycle, ADS# can be asserted
as early as one clock edge after NA# is sampled asserted.
If AHOLD is sampled asserted, ADS# is only driven in order to
perform a writeback cycle due to an inquire cycle that hits a
modified cache line.
The processor floats ADS # off the clock edge that BOFF # is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD.
Output
ADSC # has the identical function and timing as ADS#. In the
event ADS# becomes too heavily loaded due to a large fanout in
a system, ADSC # can be used to split the load across two
outputs, which can improve system timing.
Preliminary Information
Signal Descriptions
23543A/0—September 2000
Chapter 5