AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 229

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Figure 83. L1 Cache Sector Organization
9.1
Chapter 9
L1 Instruction Cache Line
L1 Data Cache Line and L2 Cache Line
Address
Tag
Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits 1 MESI Bit
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits 1 MESI Bit
MESI States in the L1 Data Cache and L2 Cache
Address
Tag
Note: L1 instruction-cache lines have only two coherency states
The state of each line in the caches is tracked by the MESI bits.
The coherency of these states or MESI bits is maintained by
internal processor snoops and external inquire cycles by the
system logic. The following four states are defined for the L1
data cache and the L2 cache:
Cache Line 0
Cache Line 1
Modified—This line has been modified and is different from
external memory.
Exclusive—In general, an exclusive line in the L1 data cache
or the L2 cache is not modified and is the same as external
memory. The exception is the case where a line exists in the
modified state in the L1 data cache and also resides in the
L2 cache. By design, the line in the L2 cache must be in the
exclusive state.
Shared—If a cache line is in the shared state it means that
the same line can exist in more than one cache system.
Invalid—The information in this line is not valid.
(valid or invalid) rather than the four MESI coherency
states of L1 data-cache and L2 cache lines. Only two states
are needed for the L1 instruction cache because these lines
are read-only.
Byte 31
Byte 31
Cache Organization
Byte 30
Byte 30
AMD-K6™-IIIE+ Embedded Processor Data Sheet
........
........
........
........
Byte 0
Byte 0
2 MESI Bits
2 MESI Bits
207