AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 143

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
5.34
Pin Attribute
Summary
Driven and Floated
Chapter 5
M/IO# (Memory or I/O)
Output
The processor drives M/IO# during a bus cycle to indicate
whether it is addressing the memory or I/O space. If M/IO# = 1,
the processor is addressing memory or a memory-mapped I/O
port as the result of an instruction fetch or an instruction that
loads or stores data. If M/IO# = 0, the processor is addressing an
I/O port during the execution of an I/O instruction. In addition,
M/IO# is used to define other bus cycles, including interrupt
acknowledge and special cycles. See Table 23 and Table 24 on
page 142 for more details.
M/IO# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted. M/IO# is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
M/IO# is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
121