AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 38

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
2.2
Cache
Figure 2. Cache Sector Organization
16
Tag Address
Cache, Instruction Prefetch, and Predecode Bits
Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
The writeback level-one (L1) cache on the AMD-K6-IIIE+
processor is organized as a separate 32-Kbyte instruction cache
and a 32-Kbyte data cache with two-way set associativity.
The level-two (L2) cache is 256 Kbytes, and is organized as a
unified, four-way set-associative cache. The cache line size is 32
bytes, and lines are fetched from external memory using an
efficient pipelined burst transaction.
As the L1 instruction cache is filled from the L2 cache or from
external memory, each instruction byte is analyzed for
instruction boundaries using predecoding logic. Predecoding
annotates information (5 bits per byte) to each instruction byte
that later enables the decoders to efficiently decode multiple
instructions simultaneously.
The processor cache design takes advantage of a sectored
organization (see Figure 2). Each sector consists of 64 bytes
configured as two 32-byte cache lines. The two cache lines of a
sector share a common tag but have separate pairs of MESI
(Modified, Exclusive, Shared, Invalid) bits that track the state
of each cache line.
Two forms of cache misses and associated cache fills can take
place—a tag-miss cache fill and a tag-hit cache fill.
Tag-Miss Cache Fill—The L1 cache miss is due to a tag
mismatch, in which case the required cache line is filled
either from the L2 cache or from external memory, and the
L1 cache line within the sector that was not required is
marked as invalid.
Tag-Hit Cache Fill—The address matches the tag, but the
requested cache line is marked as invalid. The required L1
cache line is filled from the L2 cache or from external
memory, and the L1 cache line within the sector that is not
required remains in the same cache state.
Preliminary Information
Internal Architecture
23543A/0—September 2000
Chapter 2