AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 202

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
AHOLD Restriction
180
When the system logic drives an AHOLD-initiated inquire
cycle, it must assert AHOLD for at least two clocks before it
asserts EADS#. This requirement guarantees the processor
recognizes and responds to the inquire cycle properly. The
processor’s 32 address bus drivers turn on almost immediately
after AHOLD is sampled negated. If the processor switches the
data bus (D[63:0] and DP[7:0]) during a write cycle off the same
clock edge that switches the address bus (A[31:3] and AP), the
processor switches 102 drivers simultaneously, which can lead
to ground-bounce spikes. Therefore, before negating AHOLD
the following restrictions must be observed by the system logic:
When the system logic negates AHOLD during a write cycle,
it must ensure that AHOLD is not sampled negated on the
clock edge on which BRDY# is sampled asserted (See
Figure 72 on page 181).
When the system logic negates AHOLD during a writeback
cycle, it must ensure that AHOLD is not sampled negated on
the clock edge on which ADS# is negated (See Figure 72).
When a write cycle is pipelined into a read cycle, AHOLD
must not be sampled negated on the clock edge after the
clock edge on which the last BRDY# of the read cycle is
sampled asserted to avoid the processor simultaneously
driving the data bus (for the pending write cycle) and the
address bus off this same clock edge.
Preliminary Information
Bus Cycles
23543A/0—September 2000
Chapter 7