AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 186

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Burst Writeback
164
Figure 63 on page 165 shows a burst read followed by a
writeback transaction. The AMD-K6-IIIE+ processor initiates
writebacks under the following conditions:
The processor drives writeback cycles during inquire or cache
flush cycles. The writeback shown in Figure 63 is caused by a
cache-line replacement. The processor completes the burst read
cycle that fills the cache line. Immediately following the burst
read cycle is the burst writeback cycle that represents the
modified line to be written back to memory. D[63:0] are driven
one clock edge after the clock edge on which ADS# is asserted
and are subsequently changed off the clock edge on which each
of the four BRDY# signals of the burst cycle are sampled
asserted.
Replacement—If a cache-line fill is initiated for a cache line
currently filled with valid entries, the processor selects a
line for replacement based on a least-recently-used (LRU)
algorithm for the L1 instruction cache and the L2 cache, and
a least-recently-allocated (LRA) algorithm for the L1 data
cache. Before a replacement is made to a L1 data cache or L2
cache line that is in the modified state, the modified line is
scheduled to be written back to memory.
Internal Snoop—The processor snoops its L1 instruction
cache during read or write misses to its L1 data cache, and it
snoops its L1 data cache during read misses to its L1
instruction cache. This snooping is performed to determine
whether the same address is stored in both caches, a
situation that is taken to imply the occurrence of
self-modifying code. If an internal snoop hits a L1 data cache
line in the modified state, the line is written back to memory
before being invalidated.
WBINVD Instruction—When the processor executes a
WBINVD instruction, it writes back all modified lines in the
L1 data cache and L2 cache, and then invalidates all lines in
all caches.
Cache
asserted, it executes a flush acknowledge special cycle and
writes back all modified lines in the L1 data cache and L2
cache, and then invalidates all lines in all caches.
Preliminary Information
Flush—When
Bus Cycles
the
processor
samples
23543A/0—September 2000
FLUSH#
Chapter 7