AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 47

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
2.6
Branch History Table
Chapter 2
Branch-Prediction Logic
Sophisticated branch logic that can minimize or hide the impact
of changes in program flow is designed into the AMD-K6-IIIE+
processor. Branches in x86 code fit into two categories:
Typical applications have up to 10% of unconditional branches
a n d a n o t h e r 1 0 % t o 2 0 % c o n d i t i o n a l b ra n ch e s . Th e
AMD-K6-IIIE+ processor branch logic has been designed to
handle this type of program behavior and to minimize its
negative effects on instruction execution, such as stalls due to
delayed instruction fetching and the draining of the processor
pipeline. The branch logic contains an 8192-entry branch
history table, a 16-entry by 16-byte branch target cache, a
16-entry return address stack, and a branch execution unit.
The AMD-K6-IIIE+ processor handles unconditional branches
without any penalty by redirecting instruction fetching to the
target address of the unconditional branch. However,
c o n d i t i o n a l b ra n che s re q u i re t h e u se o f t h e dy n a m i c
branch-prediction mechanism built into the AMD-K6-IIIE+
processor.
A two-level adaptive history algorithm is implemented in an
8192-entry branch history table. This table stores executed
branch information, predicts individual branches, and predicts
the behavior of groups of branches.
To a c c o m m o d a t e t h e l a rg e b ra n ch h i s t o ry t a b l e , t h e
AMD-K6-IIIE+ processor does not store predicted target
addresses. Instead, the branch target addresses are calculated
on-the-fly using ALUs during the decode stage. The adders
calculate all possible target addresses before the instructions
are fully decoded and the processor chooses which addresses
are valid.
Unconditional branches always change program flow (that is,
the branches are always taken)
Conditional branches may or may not divert program flow
(that is, the branches are taken or not-taken). When a
conditional branch is not taken, the processor simply
continues decoding and executing the next instructions in
memory.
Internal Architecture
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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