AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 238

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Write to a Cacheable
Page
Write to a Sector
Write Allocate Limit
216
Due to the nature of software, memory accesses tend to occur in
proximity of each other (principle of locality). The likelihood of
additional write hits to the write-allocated cache line is high.
Write allocates that hit the L2 cache increase performance by
avoiding accesses to the system bus.
The following is a description of three mechanisms by which the
AMD-K6-IIIE+ processor performs write allocations. A write
al lo c at e is p e r fo rm e d wh en a ny o n e o r m o re of t h e se
mechanisms indicates that a pending write is to a cacheable
area of memory.
Every time the processor completes a L1 cache line fill, the
address of the page in which the cache line resides is saved in
the Cacheability Control Register (CCR). The page address of
subsequent write cycles is compared with the page address
stored in the CCR. If the two addresses are equal, then the
processor performs a write allocate because the page has
already been determined to be cacheable.
When the processor performs a L1 cache line fill from a
different page than the address saved in the CCR, the CCR is
updated with the new page address.
If the address of a pending write cycle matches the tag address
of a valid L1 cache sector, but the addressed cache line within
the sector is marked invalid (a sector hit but a cache line miss),
then the processor performs a write allocate. The pending write
cycle is determined to be cacheable because the sector hit
indicates the presence of at least one valid cache line in the
sector. The two cache lines within a sector are guaranteed by
design to be within the same page.
The AMD-K6-IIIE+ processor uses two mechanisms that are
programmable within the Write Handling Control Register
(WHCR) to enable write allocations for write cycles that
address a definable area, or a special 1-Mbyte memory area.
The WHCR contains two fields —the Write Allocate Enable
Limit (WAELIM) field, and the Write Allocate Enable
15-to-16-Mbyte (WAE15M) bit (see Figure 84).
Preliminary Information
Cache Organization
23543A/0—September 2000
Chapter 9