AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 322

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
16.4
Valid Delay and Float
Timing
Setup and Hold
Timing
16.5
Table 64. Output Delay Timings for 100-MHz Bus Operation
300
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
15
16
17
18
6
7
8
9
Parameter Description
A[31:3] Valid Delay
A[31:3] Float Delay
ADS# Valid Delay
ADS# Float Delay
ADSC# Valid Delay
ADSC# Float Delay
AP Valid Delay
AP Float Delay
APCHK# Valid Delay
BE[7:0]# Valid Delay
BE[7:0]# Float Delay
BREQ Valid Delay
CACHE# Valid Delay
Valid Delay, Float, Setup, and Hold Timings
Output Delay Timings for 100-MHz Bus Operation
The maximum valid delay timings are provided to allow a
system designer to determine if setup times to the system logic
can be met. Likewise, the minimum valid delay timings are used
to analyze hold times to the system logic.
The setup and hold time requirements for the AMD-K6-IIIE+
processor input signals must be met by the system logic to
assure the proper operation of the AMD-K6-IIIE+ processor.
Valid delay and float timings are given for output signals
during functional operation and are given relative to the
rising edge of CLK.
During boundary-scan testing, valid delay and float timings
for output signals are with respect to the falling edge of
TCK.
The setup and hold timings during functional and
boundary-scan test mode are given relative to the rising
edge of CLK and TCK, respectively.
Signal Switching Characteristics
Preliminary Information
1.1 ns
1.0 ns
1.0 ns
1.0 ns
1.0 ns
1.0 ns
1.0 ns
1.0 ns
Min
Preliminary Data
4.0 ns
4.0 ns
7.0 ns
4.0 ns
4.0 ns
5.5 ns
7.0 ns
4.5 ns
7.0 ns
4.0 ns
4.0 ns
7.0 ns
7.0 ns
Max
23543A/0—September 2000
Chapter 16
Figure
106
107
106
107
106
107
106
107
106
106
107
106
106