AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 72

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Page Flush/Invalidate
Register (PFIR)
Figure 39. Page Flush/Invalidate Register (PFIR)
Level-2 Cache Array
Access Register
(L2AAR)
50
Symbol
63
LINPAGE
PF
F/I
20-bit Linear Page Address
Page Fault Occurred
Flush/Invalidate Command
Reserved
Description
T h e A M D -K 6 -I I I E + p r o c e s s o r c o n t a i n s t h e Pa g e
Flush/Invalidate Register (PFIR) (see Figure 39) that allows
cache invalidation and optional flushing of a specific 4-Kbyte
page from the linear address space. For more detailed
information on PFIR, see “Page Flush/Invalidate Register
(PFIR)” on page 223. The PFIR register is MSR C000_0088h.
The AMD-K6-IIIE+ processor provides the L2AAR register that
allows for direct access to the L2 cache and L2 tag arrays. The
L2AAR register is MSR C000_0089h.
The operation that is performed on the L2 cache is a function of
the instruction executed — RDMSR or WRMSR — and the
contents of the EDX register. The EDX register specifies the
location of the access, and whether the access is to the L2 cache
data or tags (refer to Figure 40).
Bit
31-12
8
0
Preliminary Information
Software Environment
32
31
LINPAGE
12
11
9 8 7
23543A/0—September 2000
P
F
1 0
Chapter 3
F
/
I