AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 128

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.17
Pin Attribute
Summary
Driven and Floated
106
D/C# (Data/Code)
Output
The processor drives D/C # during a memory bus cycle to
indicate whether it is addressing data or executable code. D/C#
is also used to define other bus cycles, including interrupt
acknowledge and special cycles. See Table 23 and Table 24 on
page 142 for more details.
D/C# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA # or the last
expected BRDY # of the cycle is sampled asserted. D/C # is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
D/C # is floated off the clock edge that BOFF # is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
Preliminary Information
Signal Descriptions
23543A/0—September 2000
Chapter 5