AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 233

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Table 38. CACHE# Signal Generation
Notes:
1. WC and UC refer to Write-Combining and Uncacheable Memory Ranges as defined in the UWCCR.
Cache-Related Signals
9.4
L1 and L2 Cache
Disabling
Chapter 9
Cycle Type
Writebacks
Unlocked Reads
Locked Reads
Single Writes
Any Cycle Except Writebacks
Any Cycle Except Writebacks
Any Cycle Except Writebacks
Cache Disabling and Flushing
Complete descriptions of the signals that control cacheability
and cache coherency are given on the following pages:
To completely disable all accesses to the L1 and the L2 caches,
the CD bit must be set to 1 and the caches must be completely
flushed. There are three different methods for flushing the
caches. The first method relies on the system logic and the
other two methods rely on software.
CI Bit of TR12
CACHE#—page 105
EADS#—page 109
FLUSH#—page 112
HIT#—page 113
HITM#—page 113
INV—page 118
KEN#—page 119
PCD—page 124
PWT—page 126
WB/WT#—page 139
For the system logic to flush the caches, the processor must
sample FLUSH# asserted. In this method, the processor
writes back any L1 data cache and L2 cache lines that are in
X
0
X
X
1
X
X
Cache Organization
PCD Signal
X
0
X
X
X
1
X
AMD-K6™-IIIE+ Embedded Processor Data Sheet
Access Within WC/UC Range
X
0
X
X
X
X
1
1
CACHE#
High
High
High
High
High
Low
Low
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