AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 247

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Table 40. Valid L1 and L2 Cache States and Effect of Inquire Cycles
Notes:
1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and
2. Writeback cycles to the bus are 32-byte burst writes.
3. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in
Chapter 9
Cache State Before Inquire
are treated as “valid” states.
the modified state in the L2 cache.
L1
E
M
M
E
E
S
S
I
I
I
I
3
L2
M
M
E
S
E
E
S
I
I
I
I
3
Table 40 shows all possible cache-line states before and after
inquire cycles.
1
Memory Access
Writeback L2 to bus
–
–
–
Writeback L2 to bus
–
–
Writeback L1 to bus
Writeback L1 to bus
–
–
Cache Organization
2
AMD-K6™-IIIE+ Embedded Processor Data Sheet
L1
S
S
S
S
S
S
S
I
I
I
I
INV = 0
Cache State After Inquire
L2
S
S
S
S
S
S
I
I
I
I
I
L1
I
I
I
I
I
I
I
I
I
I
I
INV = 1
L2
I
I
I
I
I
I
I
I
I
I
I
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