AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 144

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.35
Pin Attribute
Summary
Sampled
122
NA# (Next Address)
Input
System logic asserts NA# to indicate to the processor that it is
ready to accept another bus cycle pipelined into the previous
bus cycle. ADS#, along with address and status signals, can be
asserted as early as one clock edge after NA# is sampled
asserted if the processor is prepared to start a new cycle.
Because the processor allows a maximum of two cycles to be in
progress at a time, the assertion of NA# is sampled while two
cycles are in progress, but ADS# is not asserted until the
completion of the first cycle.
NA# is sampled every clock edge during bus cycles, starting one
clock edge after the clock edge that negates ADS#, until the last
expected BRDY# of the last executed cycle is sampled asserted
(with the exception of the clock edge after the clock edge that
negates the ADS# for a second pending cycle). Because the
processor latches NA# when sampled, the system logic only
needs to assert NA# for one clock.
Preliminary Information
Signal Descriptions
23543A/0—September 2000
Chapter 5