AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 288

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Figure 93. L2 Tag or Data Location for the AMD-K6™-IIIE+ Processor—EDX
L2 Cache Data Reads
266
Symbol
31
Set
Line
Octet
Dword
Description
Selects the desired cache set
Selects Line1 (1) or Line0 (0)
Selects one of four octets
Selects upper (1) or lower (0) dword
Reserved
page 266 describes the operation that is performed based on
the instruction and the T/D bit.
Table 53. Tag versus Data Selector
When the L2AAR is read or written, EDX is left unchanged.
This facilitates multiple accesses when testing the entire
cache/tag array.
If the L2 cache data is read (as opposed to reading the tag
information), the result (dword) is placed in EAX in the format
Instruction
WRMSR
WRMSR
RDMSR
RDMSR
21
20 19
D
T
/
Preliminary Information
Bit
15-6
5
4-3
2
(EDX[20])
18
T/D
17 16
Test and Debug
0
1
0
1
Way
15
Operation
Read dword from L2 data array into EAX. Dword location
is specified by EDX.
Read tag, line state and LRU information from L2 tag array
into EAX. Location of tag is specified by EDX.
Write dword to the L2 data array using data in EAX. Dword
location is specified by EDX.
Write tag, line state and LRU information into L2 tag array
from EAX. Location of tag is specified by EDX.
Symbol
T/D
Way
Set
Description
Selects Tag (1) or Data (0) access
Selects desired cache way
6
5
L
n
e
23543A/0—September 2000
i
4
Octet
3 2 1
D
w
o
d
r
Bit
20
17-16
Chapter 13
0