AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 210

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Interrupt
Acknowledge
188
In response to recognizing the system’s maskable interrupt
(INTR), the processor drives an interrupt acknowledge cycle at
t h e n e x t i n s t r u c t i o n b o u n d a ry. D u r i n g a n i n t e r r u p t
acknowledge cycle, the processor drives a locked pair of read
cycles as shown in Figure 76 on page 189. The first read cycle is
not functional, and the second read cycle returns the interrupt
number on D[7:0] (00h–FFh). Table 32 shows the state of the
signals during an interrupt acknowledge cycle.
Table 32. Interrupt Acknowledge Operation Definition
The system logic can drive INTR either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks. To ensure it
is recognized, INTR must remain asserted until an interrupt
acknowledge sequence is complete.
Processor Outputs
D/C#
M/IO#
W/R#
BE[7:0]#
A[31:3]
D[63:0]
Preliminary Information
Bus Cycles
First Bus Cycle
Low
Low
Low
EFh
0000_0000h
(ignored)
Second Bus Cycle
Low
Low
Low
FEh (low byte enabled)
0000_0000h
Interrupt number expected from interrupt con-
troller on D[7:0]
23543A/0—September 2000
Chapter 7