AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 69

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Extended Feature
Enable Register
(EFER)
Figure 34. Extended Feature Enable Register (EFER)
Table 6.
Chapter 3
63–5
3-2
Bit
4
1
0
Symbol
63
L2D
EWBEC
DPE
SCE
Description
Reserved
L2D
EWBE Control
(EWBEC)
Data Prefetch
Enable (DPE)
System Call
Extension (SCE)
Extended Feature Enable Register (EFER) Definition
Reserved
L2 Cache Disable
EWBE# Control
Data Prefetch Enable
System Call Extension
Description
The Extended Feature Enable Register (EFER) contains the
control bits that enable the extended features of the processor.
Figure 34 shows the format of the EFER register, and Table 6
defines the function of each bit of the EFER register. The EFER
register is MSR C000_0080h.
For more information about the EWBEC bits, see “EWBE#
Control” on page 229.
R/W Function
R/W
R/W
R/W
R/W
R
Writing a 1 to any reserved bit causes a general protection fault to occur. All reserved bits
are always read as 0.
If L2D is set to 1, the L2 cache is completely disabled. This bit is provided for debug and
testing purposes. For normal operation and maximum performance, this bit must be set
to 0 (this is the default setting following reset).
This 2-bit field controls the behavior of the processor with respect to the ordering of write
cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE Disable (GEWBED)
and Speculative EWBE Disable (SEWBED), respectively.
DPE must be set to 1 to enable data prefetching (this is the default setting following
reset). If enabled, cache misses initiated by a memory read within a 32-byte line are
conditionally followed by cache-line fetches of the other line in the 64-byte sector.
SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions.
Bit
4
3-2
1
0
Software Environment
AMD-K6™-IIIE+ Embedded Processor Data Sheet
5
D
4
L
2
EWBEC
3
2
D
P
E
1
C
0
S
E
47