AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 287

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Figure 91. L2 Cache Organization for AMD-K6™-IIIE+ Processor
Figure 92. L2 Cache Sector and Line Organization
Chapter 13
Set 1023
Set 0
Octet 2
Octet 3
Octet 0
Octet 1
Line1/MESI
64 bytes
Way 0
Line0/MESI
Upper Dword
Figure 92 shows the L2 cache sector and line organization. If bit
5 of the address of a cache line equals 1, then this cache line is
stored in Line 1 of a sector. Similarly, if bit 5 of the address of a
cache line equals 0, then this cache line is stored in Line 0 of a
sector.
The L2AAR register is MSR C000_0089h. The operation that is
performed on the L2 cache is a function of the instruction
executed—RDMSR or WRMSR—and the contents of the EDX
register. The EDX register specifies the location of the access,
and whether the access is to the L2 cache data or tags (refer to
Figure 93 on page 266). Bit 20 of EDX (T/D) determines
whether the access is to the L2 cache data or tag. Table 53 on
Tag/LRU
Line 1
Line1/MESI
Lower Dword
64 bytes
Way 1
Line0/MESI
Test and Debug
Tag/LRU
Sector
AMD-K6™-IIIE+ Embedded Processor Data Sheet
Line1/MESI
Upper Dword
64 bytes
Way 2
Line0/MESI
Tag/LRU
Line 0
Lower Dword
Line1/MESI
64 bytes
Way 3
Line0/MESI
Tag/LRU
265