AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 243

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
9.10
Table 39. L1 and L2 Cache States for Read and Write Accesses
Notes:
1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and
2. The final MESI state assumes that the state of the WB/WT# signal remains the same for all accesses to a particular cache line.
3. If CACHE# is driven Low and KEN# is sampled asserted.
4. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. If PWT is driven High or
Chapter 9
Cache
Read
Cache
Write
are treated as “valid” states.
WB/WT# is sampled Low, the line is cached in the shared (writethrough) state.
Type
Read Miss L1,
Read Miss L2
Read Hit L1
Read Miss L1,
Read Hit L2
Write Miss L1
Write Miss L2
Write Hit L1
Write Miss L1
Write Hit L2
Cache States
Cache State Before Access
E or M
L1
M
E
S
S
S
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Table 39 shows all the possible cache-line states before and
after program-generated accesses to individual cache lines.
L2
M
M
M
M
–
–
–
E
S
S
–
E
S
E
S
I
I
I
I
I
I
Cache Organization
1
Access Type
Single read from bus
Burst read from bus, fill L1 and L2
–
–
–
Fill L1
Fill L1
Fill L1
Fill L1
Single write to bus
Burst read from bus, fill L1 and L2, write to L1
Burst read from bus, fill L1 and L2, write to
L1 and L2, single write to bus
Write to L1,
single write to bus
Write to L1 and L2,
single write to bus
Write to L1
Write to L2
Write to L2, single write to bus
Write to L2
Fill L1, write to L1
Write to L2, single write to bus
Fill L1, write to L1
6
6
AMD-K6™-IIIE+ Embedded Processor Data Sheet
7
7
6
7
6
7
3
7
Cache State After Access
S or E
S or E
S or E
S or E
L1
M
E
S
M
M
M
M
M
E
S
E
S
I
I
I
I
I
5
9
8
MESI State
4
4
4
4
S or E
S or E
S or E
S or E
2
M
L2
E
S
M
M
–
–
–
E
S
E
–
E
E
I
I
I
8
9
5
221
4
4
4
4