AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 13

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
List of Tables
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Execution Latency and Throughput of Execution Units . . . . . 23
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
General-Purpose Register Doubleword, Word, and Byte
Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AMD-K6™-IIIE+ Processor Model-Specific Registers . . . . . . . 44
Extended Feature Enable Register (EFER) Definition . . . . . . 47
SYSCALL/SYSRET Target Address Register (STAR)
Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 54
Application Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
System Segment and Gate Types . . . . . . . . . . . . . . . . . . . . . . . . 61
Summary of Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . 62
Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MMX™ Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3DNow!™ Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3DNow!™ Technology DSP Extensions . . . . . . . . . . . . . . . . . . . 90
Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . 101
Output Pin Float Conditions for VCC2 High/Low. . . . . . . . . . 136
Input Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Input/Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . 141
Test Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Bus Cycle Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Enhanced Power Management Register (EPMR) Definition 145
EPM 16-Byte I/O Block Definition . . . . . . . . . . . . . . . . . . . . . . 146
Bus Divisor and Voltage ID Control (BVC) Definition . . . . . . 147
Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . 149
Bus-Cycle Order During Misaligned Memory Transfers . . . . 160
A[4:3] Address-Generation Sequence During Bursts . . . . . . . 162
Bus-Cycle Order During Misaligned I/O Transfers . . . . . . . . . 167
Interrupt Acknowledge Operation Definition. . . . . . . . . . . . . 188
Encodings for Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . 190
Output Signal State After RESET . . . . . . . . . . . . . . . . . . . . . . 200
Register State After RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
PWT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
PCD Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
CACHE# Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
L1 and L2 Cache States for Read and Write Accesses . . . . . . 221
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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