AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 40

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
Figure 3. The Instruction Buffer
Instruction Decode
18
Return Address Stack
32-Kbyte Level-One
Instruction Cache
Address Adders
Branch Target
16 x 16 Bytes
(two bytes) organization. Therefore, instructions are loaded and
replaced with word granularity. When a control transfer
occurs — such as a JMP instruction — the entire instruction
buffer is flushed and reloaded with a new set of 16 instruction
bytes.
The AMD-K6-IIIE+ processor decode logic is designed to
decode multiple x86 instructions per clock (see Figure 4 on
page 19). The decode logic accepts x86 instruction bytes and
their predecode bits from the instruction buffer, locates the
actual instr uction bo undaries, and genera tes RI SC86
operations from these x86 instructions.
RISC86 operations are fixed-length internal instructions. Most
RISC86 operations execute in a single clock. RISC86 operations
are combined to perform every function of the x86 instruction
set. Some x86 instructions are decoded into as few as zero
RISC86 operations — for instance a NOP — or one RISC86
Preliminary Information
16 Bytes
Internal Architecture
16 Sets of Predecode Bits
Instruction Buffer
16 Instruction Bytes
Fetch Unit
plus
2:1
16 Bytes
Branch-Target Cache
16 x 16 Bytes
23543A/0—September 2000
Chapter 2