AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 141

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
5.32
Pin Attribute
Summary
Sampled
Chapter 5
KEN# (Cache Enable)
Input
If KEN # is sampled asserted, it indicates that the address
presented by the processor is cacheable. If KEN # is sampled
asserted and the processor intends to perform a cache-line fill
(signified by the assertion of CACHE#), the processor executes
a 32-byte burst read cycle and expects to sample BRDY #
during a read cycle, a single-transfer cycle is executed and the
processor does not cache the data. For write cycles, CACHE# is
asserted to indicate the current bus cycle is a modified
cache-line writeback. KEN# is ignored during writebacks.
If PCD is asserted during a bus cycle, the processor does not
cache any data read during that cycle, regardless of the state of
KEN#. See “PCD (Page Cache Disable)” on page 124 for more
details.
If the processor has sampled the state of KEN# during a cycle,
and that cycle is aborted due to the sampling of BOFF #
asserted, the system logic must ensure that KEN# is sampled in
the same state when the processor restarts the aborted cycle.
KEN# is sampled on the clock edge on which the first BRDY# or
NA # of a read cycle is sampled asserted. If the read cycle is a
burst, KEN # is ignored during the last three assertions of
BRDY #. KEN # is sampled during read cycles only when
CACHE# is asserted.
asserted a total of four times. If KEN # is sampled negated
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
119