LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 122

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
9.5 Register description
Table 101. GPIO register map (local bus accessible registers - enhanced GPIO features)
[1]
UM10360
User manual
Generic
Name
FIODIR
FIOMASK Fast Mask register for port. Writes, sets, clears, and reads to
FIOPIN
FIOSET
FIOCLR
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Description
Fast GPIO Port Direction control register. This register
individually controls the direction of each port pin.
port (done via writes to FIOPIN, FIOSET, and FIOCLR, and
reads of FIOPIN) alter or return only the bits enabled by zeros
in this register.
Fast Port Pin value register using FIOMASK. The current state
of digital port pins can be read from this register, regardless of
pin direction or alternate function selection (as long as pins are
not configured as an input to ADC). The value read is masked
by ANDing with inverted FIOMASK. Writing to this register
places corresponding values in all bits enabled by zeros in
FIOMASK.
Important: if an FIOPIN register is read, its bit(s) masked with
1 in the FIOMASK register will be read as 0 regardless of the
physical pin state.
Fast Port Output Set register using FIOMASK. This register
controls the state of output pins. Writing 1s produces highs at
the corresponding port pins. Writing 0s has no effect. Reading
this register returns the current contents of the port output
register. Only bits enabled by 0 in FIOMASK can be altered.
Fast Port Output Clear register using FIOMASK. This register
controls the state of output pins. Writing 1s produces lows at
the corresponding port pins. Writing 0s has no effect. Only bits
enabled by 0 in FIOMASK can be altered.
Due to compatibility requirements with the LPC2300 series ARM7-based products, the
LPC17xx implements portions of five 32-bit General Purpose I/O ports. Details on a
specific GPIO port usage can be found in
The registers in
GPIO ports. These registers are located on an AHB bus for fast read and write timing.
They can all be accessed in byte, half-word, and word sizes. A mask register allows
access to a group of bits in a single GPIO port independently from other bits in the same
port.
All information provided in this document is subject to legal disclaimers.
Table 101
Rev. 2 — 19 August 2010
represent the enhanced GPIO features available on all of the
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
Section
Access Reset
R/W
R/W
R/W
R/W
WO
8.3.
value
0
0
0
0
0
[1]
FIO0MASK - 0x2009 C010
PORTn Register
Name & Address
FIO0DIR - 0x2009 C000
FIO1DIR - 0x2009 C020
FIO2DIR - 0x2009 C040
FIO3DIR - 0x2009 C060
FIO4DIR - 0x2009 C080
FIO1MASK - 0x2009 C030
FIO2MASK - 0x2009 C050
FIO3MASK - 0x2009 C070
FIO4MASK - 0x2009 C090
FIO0PIN - 0x2009 C014
FIO1PIN - 0x2009 C034
FIO2PIN - 0x2009 C054
FIO3PIN - 0x2009 C074
FIO4PIN - 0x2009 C094
FIO0SET - 0x2009 C018
FIO1SET - 0x2009 C038
FIO2SET - 0x2009 C058
FIO3SET - 0x2009 C078
FIO4SET - 0x2009 C098
FIO0CLR - 0x2009 C01C
FIO1CLR - 0x2009 C03C
FIO2CLR - 0x2009 C05C
FIO3CLR - 0x2009 C07C
FIO4CLR - 0x2009 C09C
UM10360
© NXP B.V. 2010. All rights reserved.
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