LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 133
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- OM11043 PDF datasheet
- LPC1767FBD100551 PDF datasheet #2
- LPC1767FBD100551 PDF datasheet #3
- LPC1769FBD100551 PDF datasheet #4
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- Download datasheet (6Mb)
NXP Semiconductors
UM10360
User manual
9.5.6.4 GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - 0x4002 8094)
Table 115. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit
[1]
Each bit in these read-write registers enables the falling edge interrupt for the
corresponding GPIO port 0 pin.
Table 116. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094)
Bit
12
13
31:14 -
Bit
0
1
2
3
4
5
6
7
8
9
10
11
14:12 -
15
16
17
18
19
20
21
22
23
24
25
26
27
Not available on 80-pin package.
Symbol
P2.12ER
P2.13ER
Symbol
P0.0EF
P0.1EF
P0.2EF
P0.3EF
P0.4EF
P0.5EF
P0.6EF
P0.7EF
P0.8EF
P0.9EF
P0.10EF
P0.11EF
P0.15EF
P0.16EF
P0.17EF
P0.18EF
P0.19EF
P0.20EF
P0.21EF
P0.22EF
P0.23EF
P0.24EF
P0.25EF
P0.26EF
P0.27EF
description
bit description
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
All information provided in this document is subject to legal disclaimers.
Value Description
Value Description
0
1
Rev. 2 — 19 August 2010
Enable rising edge interrupt for P2.12.
Enable rising edge interrupt for P2.13.
Reserved.
Enable falling edge interrupt for P0.0
Falling edge interrupt is disabled on P0.0.
Falling edge interrupt is enabled on P0.0.
Enable falling edge interrupt for P0.1.
Enable falling edge interrupt for P0.2.
Enable falling edge interrupt for P0.3.
Enable falling edge interrupt for P0.4.
Enable falling edge interrupt for P0.5.
Enable falling edge interrupt for P0.6.
Enable falling edge interrupt for P0.7.
Enable falling edge interrupt for P0.8.
Enable falling edge interrupt for P0.9.
Enable falling edge interrupt for P0.10.
Enable falling edge interrupt for P0.11.
Reserved.
Enable falling edge interrupt for P0.15.
Enable falling edge interrupt for P0.16.
Enable falling edge interrupt for P0.17.
Enable falling edge interrupt for P0.18.
Enable falling edge interrupt for P0.19.
Enable falling edge interrupt for P0.20.
Enable falling edge interrupt for P0.21.
Enable falling edge interrupt for P0.22.
Enable falling edge interrupt for P0.23.
Enable falling edge interrupt for P0.24.
Enable falling edge interrupt for P0.25.
Enable falling edge interrupt for P0.26.
Enable falling edge interrupt for P0.27.
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
UM10360
© NXP B.V. 2010. All rights reserved.
133 of 840
Reset
value
0
0
NA
Reset
value
0
0
0
0
0
0
NA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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