LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 812

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 502: QEI Interrupt Clear register (QEICLR -
Table 503: QEI Interrupt Enable register (QEIIE - address
Table 504: QEI Interrupt Enable Set register (QEIIES -
Table 505: QEI Interrupt Enable Clear register (QEIIEC -
Table 506. RTC pin description . . . . . . . . . . . . . . . . . . . .560
Table 507. Real-Time Clock register map . . . . . . . . . . . .561
Table 508. Interrupt Location Register (ILR - address
Table 509. Clock Control Register (CCR - address
Table 510. Counter Increment Interrupt Register (CIIR -
Table 511. Alarm Mask Register (AMR - address
Table 512. RTC Auxiliary control register (RTC_AUX -
Table 513. RTC Auxiliary Enable register (RTC_AUXEN -
Table 514. Consolidated Time register 0 (CTIME0 - address
Table 515. Consolidated Time register 1 (CTIME1 - address
Table 516. Consolidated Time register 2 (CTIME2 - address
Table 517. Time Counter relationships and values . . . . .566
Table 518. Time Counter registers . . . . . . . . . . . . . . . . .566
Table 519. Calibration register (CALIBRATION - address
Table 520. General purpose registers 0 to 4 (GPREG0 to
Table 521. Alarm registers. . . . . . . . . . . . . . . . . . . . . . . .568
Table 522. Watchdog register map . . . . . . . . . . . . . . . . .570
Table 523: Watchdog Mode register (WDMOD - address
Table 524. Watchdog operating modes selection . . . . . .571
Table 525: Watchdog Constant register (WDTC - address
Table 526: Watchdog Feed register (WDFEED - address
Table 527: Watchdog Timer Value register (WDTV - address
Table 528: Watchdog Timer Clock Source Selection register
Table 529. ADC pin description . . . . . . . . . . . . . . . . . . . .575
Table 530. ADC registers. . . . . . . . . . . . . . . . . . . . . . . . .576
Table 531: A/D Control Register (AD0CR - address
Table 532: A/D Global Data Register (AD0GDR - address
Table 533: A/D Status register (AD0INTEN - address
Table 534: A/D Data Registers (AD0DR0 to AD0DR7 -
UM10360
User manual
0x400B CFE8) bit description . . . . . . . . . . . . .555
0x400B CFE4) bit description . . . . . . . . . . . . .555
address 0x400B CFDC) bit description . . . . .556
address 0x400B CFD8) bit description . . . . . .557
0x4002 4000) bit description . . . . . . . . . . . . .562
0x4002 4008) bit description . . . . . . . . . . . . .562
address 0x4002 400C) bit description . . . . . .563
0x4002 4010) bit description . . . . . . . . . . . . .564
address 0x4002 405C) bit description . . . . . .564
address 0x4002 4058) bit description. . . . . . .564
0x4002 4014) bit description . . . . . . . . . . . . .565
0x4002 4018) bit description . . . . . . . . . . . . .565
0x4002 401C) bit description . . . . . . . . . . . . .566
0x4002 4040) bit description . . . . . . . . . . . . .567
GPREG4 - addresses 0x4002 4044 to 0x4002
4054) bit description . . . . . . . . . . . . . . . . . . . .568
0x4000 0000) bit description . . . . . . . . . . . . .571
0x4000 0004) bit description . . . . . . . . . . . . .572
0x4000 0008) bit description . . . . . . . . . . . . .572
0x4000 000C) bit description . . . . . . . . . . . . .572
(WDCLKSEL - address 0x4000 0010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .573
0x4003 4000) bit description . . . . . . . . . . . . .577
0x4003 4004) bit description . . . . . . . . . . . . .578
0x4003 400C) bit description . . . . . . . . . . . . .578
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table 535: A/D Status register (AD0STAT - address
Table 536: A/D Trim register (ADTRM - address
Table 537. D/A Pin Description . . . . . . . . . . . . . . . . . . . . 582
Table 538. DAC registers . . . . . . . . . . . . . . . . . . . . . . . . 583
Table 539: D/A Converter Register (DACR - address
Table 540. D/A Control register (DACCTRL - address
Table 541: D/A Converter register (DACR - address
Table 542. Endian behavior . . . . . . . . . . . . . . . . . . . . . . 589
Table 543. DMA Connections . . . . . . . . . . . . . . . . . . . . . 592
Table 544. GPDMA register map . . . . . . . . . . . . . . . . . . 593
Table 545. DMA Interrupt Status register (DMACIntStat -
Table 546. DMA Interrupt Terminal Count Request Status
Table 547. DMA Interrupt Terminal Count Request Clear
Table 548. DMA Interrupt Error Status register
Table 549. DMA Interrupt Error Clear register
Table 550. DMA Raw Interrupt Terminal Count Status
Table 551. DMA Raw Error Interrupt Status register
Table 552. DMA Enabled Channel register
Table 553. DMA Software Burst Request register
Table 554. DMA Software Single Request register
Table 555. DMA Software Last Burst Request register
Table 556. DMA Software Last Single Request register
Table 557. DMA Configuration register (DMACConfig -
Table 558. DMA Synchronization register (DMACSync -
Table 559. DMA Request Select register (DMAReqSel -
Table 560. DMA Channel Source Address registers
Table 561. DMA Channel Destination Address registers
Table 562. DMA Channel Linked List Item registers
Table 563. DMA channel control registers (DMACCxControl
Table 564. DMA Channel Configuration registers
Table 565. Transfer type bits . . . . . . . . . . . . . . . . . . . . . 606
0x4003 4010 to 0x4003 402C) bit description 579
0x4003 4030) bit description . . . . . . . . . . . . . 580
0x4003 4034) bit description . . . . . . . . . . . . . 580
0x4008 C000) bit description . . . . . . . . . . . . . 583
0x4008 C004) bit description . . . . . . . . . . . . . 584
0x4008 C008) bit description . . . . . . . . . . . . . 584
0x5000 4000) . . . . . . . . . . . . . . . . . . . . . . . . 595
register (DMACIntTCStat - 0x5000 4004) . . . 595
register (DMACIntTCClear - 0x5000 4008) . . 595
(DMACIntErrStat - 0x5000 400C) . . . . . . . . . 596
(DMACIntErrClr - 0x5000 4010) . . . . . . . . . . 596
register (DMACRawIntTCStat - 0x5000 4014) . .
596
(DMACRawIntErrStat - 0x5000 4018) . . . . . . 597
(DMACEnbldChns - 0x5000 401C) . . . . . . . . 597
(DMACSoftBReq - 0x5000 4020) . . . . . . . . . 597
(DMACSoftSReq - 0x5000 4024) . . . . . . . . . 598
(DMACSoftLBReq - 0x5000 4028) . . . . . . . . 598
(DMACSoftLSReq - 0x5000 402C) . . . . . . . . 599
0x5000 4030) . . . . . . . . . . . . . . . . . . . . . . . . 599
0x5000 4034) . . . . . . . . . . . . . . . . . . . . . . . . 599
0x400F C1C4) . . . . . . . . . . . . . . . . . . . . . . . . 600
(DMACCxSrcAddr - 0x5000 41x0) . . . . . . . . 601
(DMACCxDestAddr - 0x5000 41x4) . . . . . . . 601
(DMACCxLLI - 0x5000 41x8) . . . . . . . . . . . . 602
- 0x5000 41xC) . . . . . . . . . . . . . . . . . . . . . . . 603
(DMACCxConfig - 0x5000 41x0) . . . . . . . . . 605
Chapter 35: Supplementary information
UM10360
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