LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 52

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
4.6.8 PLL1 frequency calculation
4.6.9 Procedure for determining PLL1 settings
The PLL1 equations use the following parameters:
Table 35.
The PLL1 output frequency (when the PLL is both active and connected) is given by:
USBCLK = M × F
The CCO frequency can be computed as:
F
The PLL1 inputs and settings must meet the following criteria:
The PLL1 configuration for USB may be determined as follows:
Element
F
F
USBCLK
M
P
1. The desired PLL1 output frequency is USBCLK = 48 MHz.
2. Choose an oscillator frequency (F
3. Calculate the value of M to configure the MSEL1 bits. M = USBCLK / F
4. Find a value for P to configure the PSEL1 bits, such that F
CCO
•
•
•
OSC
CCO
F
USBCLK is 48 MHz.
F
multiple of F
24 MHz.
case, the possible values for M = 2, 3, or 4 (F
value written to the MSEL1 bits in PLL1CFG is M − 1 (see
frequency limits of 156 MHz to 320 MHz. F
2 × P. It follows that P = 2 is the only P value to yield F
value written to the PSEL1 bits in PLL1CFG is ‘01’ for P = 2 (see
OSC
CCO
= USBCLK × 2 × P or F
is in the range of 10 MHz to 25 MHz.
is in the range of 156 MHz to 320 MHz.
Elements determining PLL frequency
Description
the frequency from the crystal oscillator
the frequency of the PLL1 current controlled oscillator
the PLL1 output frequency (48 MHz for USB)
PLL1 Multiplier value from the MSEL1 bits in the PLL1CFG register
PLL1 Divider value from the PSEL1 bits in the PLL1CFG register
All information provided in this document is subject to legal disclaimers.
OSC
OSC
meaning that the possible values for F
or USBCLK = F
Rev. 2 — 19 August 2010
CCO
= F
OSC
CCO
Chapter 4: LPC17xx Clocking and power control
OSC
× M × 2 × P
). USBCLK must be the whole (non-fractional)
/ (2 × P)
CCO
OSC
is calculated using F
= 24 MHz, 16 MHz, or 12 MHz). The
CCO
OSC
CCO
Table
in the allowed range. The
are 12 MHz, 16 MHz, and
is within its defined
37).
Table
UM10360
© NXP B.V. 2010. All rights reserved.
CCO
OSC
36).
= USBCLK ×
. In this
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