LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 574

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

29.1 Basic configuration
29.2 Features
29.3 Description
UM10360
User manual
The ADC is configured using the following registers:
Basic clocking for the A/D converters is provided by the APB clock. A programmable
divider is included in each converter to scale this clock to the clock (maximum 13 MHz)
needed by the successive approximation process. A fully accurate conversion requires 65
of these clocks.
1. Power: In the PCONP register
2. Clock: In the PCLKSEL0 register
3. Pins: Enable ADC0 pins through PINSEL registers. Select the pin modes for the port
4. Interrupts: To enable interrupts in the ADC, see
5. DMA: See
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UM10360
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
Rev. 2 — 19 August 2010
Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit,
and then enable the ADC in the AD0CR register (bit PDN
ADC, first clear the PDN bit, and then clear the PCADC bit.
the ADC, see bits CLKDIV in
pins with ADC0 functions through the PINMODE registers
the NVIC using the appropriate Interrupt Set Enable register. Disable the ADC
interrupt in the NVIC using the appropriate Interrupt Set Enable register.
12-bit successive approximation analog to digital converter.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range V
12-bit conversion rate of 200 kHz.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Section
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
29.6.4. For GPDMA system connections, see
REFN
to V
Table
(Table
REFP
(Table
531.
(typically 3 V; not to exceed V
46), set the PCADC bit.
40), select PCLK_ADC. To scale the clock for
Table
535. Interrupts are enabled in
Table
(Section
531). To disable the
Table
DDA
© NXP B.V. 2010. All rights reserved.
8.5).
User manual
voltage level).
543.
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