LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 259

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
11.15.4.10 Packet_valid
11.15.4.12 MS_byte_extracted
11.15.4.13 Present_DMA_count
11.15.4.14 Message_length_position
11.15.4.15 Isochronous_packetsize_memory_address
11.15.4.11 LS_byte_extracted
This bit is used for isochronous endpoints. It indicates whether the last packet transferred
to the memory is received with errors or not. This bit is set if the packet is valid, i.e., it was
received without errors. See
261
This bit is unnecessary for non-isochronous endpoints because a DMA request is
generated only for packets without errors, and thus Packet_valid will always be set when
the request is generated.
Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of
the transfer length has been extracted. The extracted size is reflected in the
DMA_buffer_length field, bits 23:16.
Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of
the transfer size has been extracted. The size extracted is reflected in the
DMA_buffer_length field, bits 31:24. Extraction stops when LS_Byte_extracted and
MS_byte_extracted bits are set.
The number of bytes transferred by the DMA engine. The DMA engine updates this field
after completing each packet transfer.
For isochronous endpoints, Present_DMA_count is the number of packets transferred; for
non-isochronous endpoints, Present_DMA_count is the number of bytes.
Used in ATLE mode. This field gives the offset of the message length position embedded
in the incoming data packets. This is applicable only for OUT endpoints. Offset 0 indicates
that the message length starts from the first byte of the first packet.
The memory buffer address where the packet size information along with the frame
number has to be transferred or fetched. See
endpoints only.
•
•
•
DataUnderrun - Before reaching the end of the DMA buffer, the USB transfer is
terminated because a short packet is received. The DD_retired bit is also set.
DataOverrun - The end of the DMA buffer is reached in the middle of a packet
transfer. This is an error situation. The DD_retired bit is set. The present DMA count
field is equal to the value of DMA_buffer_length. The packet must be re-transmitted
from the endpoint buffer in another DMA transfer. The corresponding
EPxx_DMA_ENABLE bit in USBEpDMASt is cleared.
SystemError - The DMA transfer being serviced is terminated because of an error on
the AHB bus. The DD_retired bit is not set in this case. The corresponding
EPxx_DMA_ENABLE in USBEpDMASt is cleared. Since a system error can happen
while updating the DD, the DD fields in RAM may be unreliable.
for isochronous endpoint operation.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 11.15.6 “Isochronous endpoint operation” on page
Chapter 11: LPC17xx USB device controller
Figure
31. This is applicable to isochronous
UM10360
© NXP B.V. 2010. All rights reserved.
259 of 840