LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 184

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
frame descriptors, and sends them out as one Ethernet frame on the Ethernet connection.
When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1,
this indicates the last fragment of the frame and thus the end of the frame is found.
Update ConsumeIndex
Each time the Tx DMA manager commits a status word to memory it completes the
transmission of a descriptor and it increments the TxConsumeIndex (taking wrap around
into account) to hand the descriptor back to the device driver software. Software can
re-use the descriptor for new transmissions after hardware has handed it back.
The device driver software can keep track of the progress of the DMA manager by reading
the TxConsumeIndex register to see how far along the transmit process is. When the Tx
descriptor array is emptied completely, the TxConsumeIndex register retains its last value.
Write transmission status
After the frame has been transmitted over the RMII bus, the StatusInfo word of the frame
descriptor is updated by the DMA manager.
If the descriptor is for the last fragment of a frame (or for the whole frame if there are no
fragments), then depending on the success or failure of the frame transmission, error
flags (Error, LateCollision, ExcessiveCollision, Underrun, ExcessiveDefer, Defer) are set
in the status. The CollisionCount field is set to the number of collisions the frame incurred,
up to the Retransmission Maximum programmed in the Collision window/retry register of
the MAC.
Statuses for all but the last fragment in the frame will be written as soon as the data in the
frame has been accepted by the Tx DMA manager. Even if the descriptor is for a frame
fragment other than the last fragment, the error flags are returned via the AHB interface. If
the Ethernet block detects a transmission error during transmission of a (multi-fragment)
frame, all remaining fragments of the frame are still read via the AHB interface. After an
error, the remaining transmit data is discarded by the Ethernet block. If there are errors
during transmission of a multi-fragment frame the error statuses will be repeated until the
last fragment of the frame. Statuses for all but the last fragment in the frame will be written
as soon as the data in the frame has been accepted by the Tx DMA manager. These may
include error information if the error is detected early enough. The status for the last
fragment in the frame will only be written after the transmission has completed on the
Ethernet connection. Thus, the status for the last fragment will always reflect any error
that occurred anywhere in the frame.
The status of the last frame transmission can also be inspected by reading the TSV0 and
TSV1 registers. These registers do not report statuses on a fragment basis and do not
store information of previously sent frames. They are provided primarily for debug
purposes, because the communication between driver software and the Ethernet block
takes place through the frame descriptors. The status registers are valid as long as the
internal status of the MAC is valid and should typically only be read when the transmit and
receive processes are halted.
Transmission error handling
If an error occurs during the transmit process, the Tx DMA manager will report the error
via the transmission StatusInfo word written in the Status array and the IntStatus interrupt
status register.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
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