LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 592

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
31.4.2.3 DMA request connections
DMACTC[15:0] — DMA terminal count signals. The DMACTC signal can be used by the
DMA controller to indicate to the peripheral that the DMA transfer is complete.
The connection of the GPDMA to the supported peripheral devices depends on the DMA
functions implemented in those peripherals.
used by the supported peripherals. UART and timer DMA requests on channels 8 through
15 are chosen via the DMAREQSEL register, see
Table 543. DMA Connections
[1]
Peripheral Function
SSP0 Tx
SSP0 Rx
SSP1 Tx
SSP1 Rx
ADC
I
I
DAC
UART0 Tx / MAT0.0
UART0 Rx / MAT0.1
UART1 Tx / MAT1.0
UART1 Rx / MAT1.1
UART2 Tx / MAT2.0
UART2 Rx / MAT2.1
UART3 Tx / MAT3.0
UART3 Rx / MAT3.1
2
2
S channel 0
S channel 1
Generates an interrupt and/or DMA request depending on software setup.
All information provided in this document is subject to legal disclaimers.
DMA Single Request
Input (DMACSREQ)
0
1
2
3
4
-
-
-
-
-
-
-
-
-
-
-
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
DMA Burst Request
Input (DMACBREQ)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 543
Section
shows the DMA Request numbers
31.5.15.
DMA Request Signal
Dedicated DMA requests
Dedicated DMA requests
Dedicated DMA requests
Dedicated DMA requests
ADC interrupt request
Dedicated DMA request
Dedicated DMA request
Dedicated DMA request
Dedicated DMA requests
Dedicated DMA requests
Dedicated DMA requests
Dedicated DMA requests
Dedicated DMA requests
Dedicated DMA requests
Dedicated DMA requests
Dedicated DMA requests
UM10360
© NXP B.V. 2010. All rights reserved.
592 of 840
[1]