LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 627
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
32.7.8 Go <address> <mode>
32.7.9 Erase sector(s) <start sector number> <end sector number>
Table 579. ISP Go command
When the GO command is used, execution begins at the specified address (assuming it is
an executable address) with the device left as it was configured for the ISP code. This
means that some things are different than they would be for entering user code directly
following a chip reset. Most importantly, the main PLL will be running and connected,
configured to generate a CPU clock with a frequency of approximately 14.7456 MHz.
Table 580. ISP Erase sector command
Command
Input
Return Code CMD_SUCCESS |
Description
Example
Command
Input
Return Code CMD_SUCCESS |
Description
Example
"G 0 T<CR><LF>" branches to address 0x0000 0000.
"E 2 3<CR><LF>" erases the flash sectors 2 and 3.
G
Address: Flash or RAM address from which the code execution is to be started.
This address should be on a word boundary.
Mode (retained for backward compatibility): T (Execute program in Thumb
Mode) | A (not allowed).
ADDR_ERROR |
ADDR_NOT_MAPPED |
CMD_LOCKED |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED
This command is used to execute a program residing in RAM or flash memory. It
may not be possible to return to the ISP command handler once this command is
successfully executed. This command is blocked when any level of code read
protection is enabled.
E
Start Sector Number
End Sector Number: Should be greater than or equal to start sector number.
BUSY |
INVALID_SECTOR |
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION |
CMD_LOCKED |
PARAM_ERROR |
CODE_READ_PROTECTION_ENABLED
This command is used to erase one or more sector(s) of on-chip flash memory. This
command is blocked when code read protection level CRP3 is enabled. When code
read protection level CRP1 is enabled, individual sectors other than sector 0 can be
erased. All sectors can be erased at once in CRP1 and CRP2.
All information provided in this document is subject to legal disclaimers.
Chapter 32: LPC17xx Flash memory interface and programming
Rev. 2 — 19 August 2010
UM10360
© NXP B.V. 2010. All rights reserved.
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