LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 238

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 228. USB EP DMA Enable register (USBEpDMAEn - address 0x5000 C288) bit description
Table 229. USB EP DMA Disable register (USBEpDMADis - address 0x5000 C28C) bit description
Table 230. USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description
UM10360
User manual
Bit
0
1
31:2
Bit
0
1
31:2
Bit
0
1
Symbol
EP0_DMA_ENABLE
EP1_DMA_ENABLE
EPxx_DMA_ENABLE
EPxx_DMA_DISABLE
Symbol
EOT
NDDR
Symbol
EP0_DMA_DISABLE
EP1_DMA_DISABLE
11.10.7.6 USB EP DMA Enable register (USBEpDMAEn - 0x5000 C288)
11.10.7.7 USB EP DMA Disable register (USBEpDMADis - 0x5000 C28C)
11.10.7.8 USB DMA Interrupt Status register (USBDMAIntSt - 0x5000 C290)
Value Description
0
1
0
1
Writing one to a bit to this register will enable the DMA operation for the corresponding
endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints
EP0 and EP1. USBEpDMAEn is a write-only register.
Writing a one to a bit in this register clears the corresponding bit in USBEpDMASt. Writing
zero has no effect on the corresponding bit of USBEpDMASt. Any write to this register
clears the internal DMA_PROCEED flag. Refer to
descriptor fetch”
progress for an endpoint when its corresponding bit is cleared, the transfer is completed
before the DMA is disabled. When an error condition is detected during a DMA transfer,
the corresponding bit is cleared by hardware. USBEpDMADis is a write-only register.
Each bit of this register reflects whether any of the 32 bits in the corresponding interrupt
status register are set. USBDMAIntSt is a read-only register.
End of Transfer Interrupt bit.
All bits in the USBEoTIntSt register are 0.
At least one bit in the USBEoTIntSt is set.
New DD Request Interrupt bit.
All bits in the USBNDDRIntSt register are 0.
At least one bit in the USBNDDRIntSt is set.
Value Description
0
0
0
1
Value Description
0
0
0
1
Control endpoint OUT (DMA cannot be enabled for this endpoint and
the EP0_DMA_ENABLE bit value must be 0).
Control endpoint IN (DMA cannot be enabled for this endpoint and the
EP1_DMA_ENABLE bit must be 0).
Endpoint xx(2 ≤ xx ≤ 31) DMA enable control bit.
No effect.
Enable the DMA operation for endpoint EPxx.
Control endpoint OUT (DMA cannot be enabled for this endpoint and
the EP0_DMA_DISABLE bit value must be 0).
Control endpoint IN (DMA cannot be enabled for this endpoint and the
EP1_DMA_DISABLE bit value must be 0).
Endpoint xx (2 ≤ xx ≤ 31) DMA disable control bit.
No effect.
Disable the DMA operation for endpoint EPxx.
All information provided in this document is subject to legal disclaimers.
for more information on the DMA_PROCEED flag. If a DMA transfer is in
Rev. 2 — 19 August 2010
Chapter 11: LPC17xx USB device controller
Section 11.15.5.4 “Optimizing
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
0
0
0
Reset value
0
0
0
Reset value
0
0
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