LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 815

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
35.4 Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. PLL1 block diagram . . . . . . . . . . . . . . . . . . . . . . .48
Fig 11. PLLs and clock dividers . . . . . . . . . . . . . . . . . . . .54
Fig 12. CLKOUT selection . . . . . . . . . . . . . . . . . . . . . . . .66
Fig 13. Simplified block diagram of the flash accelerator
Fig 14. LPC176x LQFP100 pin configuration . . . . . . . . .91
Fig 15. LPC175x LQFP80 pin configuration . . . . . . . . . .91
Fig 16. Pin configuration TFBGA100 package. . . . . . . . .92
Fig 17. Ethernet block diagram . . . . . . . . . . . . . . . . . . .143
Fig 18. Ethernet packet fields . . . . . . . . . . . . . . . . . . . .145
Fig 19. Receive descriptor memory layout. . . . . . . . . . .172
Fig 20. Transmit descriptor memory layout . . . . . . . . . .175
Fig 21. Transmit example memory and registers. . . . . .186
Fig 22. Receive Example Memory and Registers . . . . .192
Fig 23. Transmit Flow Control . . . . . . . . . . . . . . . . . . . .197
Fig 24. Receive filter block diagram. . . . . . . . . . . . . . . .199
Fig 25. Receive Active/Inactive state machine . . . . . . .203
Fig 26. Transmit Active/Inactive state machine . . . . . . .204
Fig 27. USB device controller block diagram . . . . . . . . .216
Fig 28. USB MaxPacketSize register array indexing . . .232
Fig 29. Interrupt event handling . . . . . . . . . . . . . . . . . . .243
Fig 30. UDCA Head register and DMA Descriptors . . . .256
Fig 31. Isochronous OUT endpoint operation example .263
Fig 32. Data transfer in ATLE mode. . . . . . . . . . . . . . . .264
Fig 33. USB Host controller block diagram . . . . . . . . . .270
Fig 34. USB OTG controller block diagram . . . . . . . . . .274
Fig 35. USB OTG port configuration . . . . . . . . . . . . . . .275
Fig 36. USB host port configuration . . . . . . . . . . . . . . . .276
Fig 37. USB device port configuration . . . . . . . . . . . . . .276
Fig 38. USB OTG interrupt handling . . . . . . . . . . . . . . .286
Fig 39. USB OTG controller with software stack . . . . . .287
Fig 40. Hardware support for B-device switching from
Fig 41. State transitions implemented in software during
Fig 42. Hardware support for A-device switching from host
Fig 43. State transitions implemented in software during
Fig 44. Clocking and power control . . . . . . . . . . . . . . . .295
Fig 45. Auto-baud a) mode 0 and b) mode 1 waveform 311
Fig 46. Algorithm for setting UART dividers. . . . . . . . . .314
Fig 47. UART0, 2 and 3 block diagram . . . . . . . . . . . . .317
Fig 48. Auto-RTS Functional Timing . . . . . . . . . . . . . . .328
Fig 49. Auto-CTS Functional Timing . . . . . . . . . . . . . . .329
UM10360
User manual
LPC1768 simplified block diagram. . . . . . . . . . . . .8
LPC1768 block diagram, CPU and buses . . . . . . 11
LPC17xx system memory map . . . . . . . . . . . . . .13
Reset block diagram including the wake-up timer19
Example of start-up after reset. . . . . . . . . . . . . . .20
External interrupt logic . . . . . . . . . . . . . . . . . . . . .23
Clock generation for the LPC17xx . . . . . . . . . . . .29
Oscillator modes and models: a) slave mode of
operation, b) oscillation mode of operation, c)
external crystal model used for C
PLL0 block diagram . . . . . . . . . . . . . . . . . . . . . . .36
showing potential bus connections . . . . . . . . . . .68
peripheral state to host state . . . . . . . . . . . . . . .288
B-device switching from peripheral to host . . . .289
state to peripheral state . . . . . . . . . . . . . . . . . . .291
A-device switching from host to peripheral . . . .292
X1
All information provided in this document is subject to legal disclaimers.
/
X2
evaluation32
Rev. 2 — 19 August 2010
Fig 50. Auto-baud a) mode 0 and b) mode 1 waveform 334
Fig 51. Algorithm for setting UART dividers . . . . . . . . . 336
Fig 52. UART1 block diagram . . . . . . . . . . . . . . . . . . . . 342
Fig 53. CAN controller block diagram . . . . . . . . . . . . . . 345
Fig 54. Transmit buffer layout for standard and extended
Fig 55. Receive buffer layout for standard and extended
Fig 56. Global Self-Test (high-speed CAN Bus
Fig 57. Local self test (high-speed CAN Bus example). 348
Fig 58. Entry in FullCAN and individual standard identifier
Fig 59. Entry in standard identifier range table . . . . . . . 375
Fig 60. Entry in either extended identifier table . . . . . . . 376
Fig 61. ID Look-up table example explaining the search
Fig 62. Semaphore procedure for reading an auto-stored
Fig 63. FullCAN section example of the ID look-up
Fig 64. FullCAN message object layout . . . . . . . . . . . . 387
Fig 65. Normal case, no messages lost . . . . . . . . . . . . 389
Fig 66. Message lost . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Fig 67. Message gets overwritten . . . . . . . . . . . . . . . . . 390
Fig 68. Message overwritten indicated by semaphore bits
Fig 69. Message overwritten indicated by message lost392
Fig 70. Clearing message lost. . . . . . . . . . . . . . . . . . . . 393
Fig 71. Detailed example of acceptance filter tables and ID
Fig 72. ID Look-up table configuration example (no
Fig 73. ID Look-up table configuration example (FullCAN
Fig 74. SPI data transfer format (CPHA = 0 and
Fig 75. SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . 411
Fig 76. Texas Instruments Synchronous Serial Frame
Fig 77. SPI frame format with CPOL=0 and CPHA=0 (a)
Fig 78. SPI frame format with CPOL=0 and CPHA=1. . 416
Fig 79. SPI frame format with CPOL = 1 and CPHA = 0 (a)
Fig 80. SPI Frame Format with CPOL = 1 and
Fig 81. Microwire frame format (single transfer) . . . . . . 419
Fig 82. Microwire frame format (continuos transfers) . . 420
Fig 83. Microwire frame format setup and hold details . 420
Fig 84. I
Fig 85. Format in the Master Transmitter mode . . . . . . 432
Fig 86. Format of Master Receiver mode . . . . . . . . . . . 432
Fig 87. A Master Receiver switches to Master Transmitter
frame format configurations . . . . . . . . . . . . . . . 346
frame format configurations . . . . . . . . . . . . . . . 347
example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
and message lost . . . . . . . . . . . . . . . . . . . . . . . 391
index values . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
FullCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
activated and enabled) . . . . . . . . . . . . . . . . . . . 399
CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer . . . . . . . . . . . . . . . . . . . . 414
Single and b) Continuous Transfer) . . . . . . . . . 415
Single and b) Continuous Transfer) . . . . . . . . . 417
CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
after sending repeated START . . . . . . . . . . . . . 433
2
C-bus configuration. . . . . . . . . . . . . . . . . . . . . 430
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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