LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 216

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
Fig 27. USB device controller block diagram
DMA interface
(AHB master)
(AHB slave)
interface
register
11.6.1 Analog transceiver
11.6.2 Serial Interface Engine (SIE)
11.6.3 Endpoint RAM (EP_RAM)
11.6.4 EP_RAM access control
The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX
sends/receives the bi-directional D+ and D- signals of the USB bus.
The SIE implements the full USB protocol layer. It is completely hardwired for speed and
needs no firmware intervention. It handles transfer of data between the endpoint buffers in
EP_RAM and the USB bus. The functions of this block include: synchronization pattern
recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation,
PID verification/generation, address recognition, and handshake evaluation/generation.
Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated for
this purpose is called the EP_RAM. Each realized endpoint has a reserved space in the
EP_RAM. The total EP_RAM space required depends on the number of realized
endpoints, the maximum packet size of the endpoint, and whether the endpoint supports
double buffering.
The EP_RAM Access Control logic handles transfer of data from/to the EP_RAM and the
three sources that can access it: the CPU (via the Register Interface), the SIE, and the
DMA Engine.
USB DEVICE
BLOCK
INTERFACE
MASTER
INTERFACE
REGISTER
BUS
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
CONTROL
EP_RAM
ACCESS
EP_RAM
ENGINE
DMA
(4K)
Chapter 11: LPC17xx USB device controller
INTERFACE
ENGINE
SERIAL
UM10360
© NXP B.V. 2010. All rights reserved.
USB_UP_LED
USB_CONNECT
USB_D+
USB_D-
V
BUS
216 of 840