LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 132

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
9.5.6.3 GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0)
Table 114. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit
[1]
Each bit in these read-write registers enables the rising edge interrupt for the
corresponding port 2 pin.
Table 115. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit
Bit
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bit
0
1
2
3
4
5
6
7
8
9
10
11
Not available on 80-pin package.
Symbol
P0.17ER
P0.18ER
P0.19ER
P0.20ER
P0.21ER
P0.22ER
P0.23ER
P0.24ER
P0.25ER
P0.26ER
P0.27ER
P0.28ER
P0.29ER
P0.30ER
-
Symbol
P2.0ER
P2.1ER
P2.2ER
P2.3ER
P2.4ER
P2.5ER
P2.6ER
P2.7ER
P2.8ER
P2.9ER
P2.10ER
P2.11ER
description
description
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
All information provided in this document is subject to legal disclaimers.
Value Description
Value Description
0
1
Rev. 2 — 19 August 2010
Enable rising edge interrupt for P0.17.
Enable rising edge interrupt for P0.18.
Enable rising edge interrupt for P0.19.
Enable rising edge interrupt for P0.20.
Enable rising edge interrupt for P0.21.
Enable rising edge interrupt for P0.22.
Enable rising edge interrupt for P0.23.
Enable rising edge interrupt for P0.24.
Enable rising edge interrupt for P0.25.
Enable rising edge interrupt for P0.26.
Enable rising edge interrupt for P0.27.
Enable rising edge interrupt for P0.28.
Enable rising edge interrupt for P0.29.
Enable rising edge interrupt for P0.30.
Reserved.
Enable rising edge interrupt for P2.0.
Rising edge interrupt is disabled on P2.0.
Rising edge interrupt is enabled on P2.0.
Enable rising edge interrupt for P2.1.
Enable rising edge interrupt for P2.2.
Enable rising edge interrupt for P2.3.
Enable rising edge interrupt for P2.4.
Enable rising edge interrupt for P2.5.
Enable rising edge interrupt for P2.6.
Enable rising edge interrupt for P2.7.
Enable rising edge interrupt for P2.8.
Enable rising edge interrupt for P2.9.
Enable rising edge interrupt for P2.10.
Enable rising edge interrupt for P2.11.
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
UM10360
© NXP B.V. 2010. All rights reserved.
132 of 840
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NA
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0