LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 583

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
30.4 Register description
Table 538. DAC registers
[1]
Table 539: D/A Converter Register (DACR - address 0x4008 C000) bit description
UM10360
User manual
Name
DACR
DACCTRL
DACCNTVAL
Bit
5:0
15:6
16
31:17 -
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Symbol Value
-
VALUE
BIAS
[1]
30.4.1 D/A Converter Register (DACR - 0x4008 C000)
30.4.2 D/A Converter Control register (DACCTRL - 0x4008 C004)
0
1
Description
D/A Converter Register. This register contains the digital value to be
converted to analog and a power control bit.
DAC Control register. This register controls DMA and timer operation. R/W
DAC Counter Value register. This register contains the reload value for
the DAC DMA/Interrupt timer.
The DAC registers are shown in
in the PCONP register. To enable the DAC, its output must be selected to appear on the
related pin, P0.26, by configuring the PINSEL1 register. See
Select Register 1 (PINSEL1 - 0x4002
prior to accessing any DAC registers.
This read/write register includes the digital value to be converted to analog, and a bit that
trades off performance vs. power. Bits 5:0 are reserved for future, higher-resolution D/A
converters.
[1]
This read/write register enables the DMA operation and controls the DMA timer.
Description
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
After the selected settling time after this field is written with a new VALUE, the voltage on
the AOUT pin (with respect to V
The settling time of the DAC is 1 μ s max, and the maximum current is 700 μ A. This allows
a maximum update rate of 1 MHz.
The settling time of the DAC is 2.5 μ s and the maximum current is 350 μ A. This allows a
maximum update rate of 400 kHz.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The settling times noted in the description of the BIAS bit are valid for a capacitance load on the AOUT pin
not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than
the specified time. One or more graph(s) of load impedance vs. settling time will be included in the final data
sheet.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 30: LPC17xx Digital-to-Analog Converter (DAC)
SSA
Table
) is VALUE × ((V
C004)”. the DAC must be enabled in this manner
538. Note that the DAC does not have a control bit
REFP
- V
REFN
Access
R/W
R/W
)/1024) + V
Section 8.5.2 “Pin Function
Reset
value
0
0
0
REFN
UM10360
© NXP B.V. 2010. All rights reserved.
[1]
.
Address
0x4008 C000
0x4008 C004
0x4008 C008
583 of 840
Reset
Value
NA
0
0
NA