LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 564

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 511. Alarm Mask Register (AMR - address 0x4002 4010) bit description
Table 512. RTC Auxiliary control register (RTC_AUX - address 0x4002 405C) bit description
Table 513. RTC Auxiliary Enable register (RTC_AUXEN - address 0x4002 4058) bit description
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
31:8
Bit
3:0
4
31:5
Bit
3:0
4
31:5
Symbol
AMRSEC
AMRMIN
AMRHOUR When 1, the Hour value is not compared for the alarm.
AMRDOM
AMRDOW
AMRDOY
AMRMON
AMRYEAR When 1, the Year value is not compared for the alarm.
-
Symbol
-
RTC_OSCF RTC Oscillator Fail detect flag.
-
Symbol
-
RTC_OSCFEN Oscillator Fail Detect interrupt enable.
-
27.6.2.5 RTC Auxiliary control register (RTC_AUX - 0x4002 405C)
27.6.2.6 RTC Auxiliary Enable register (RTC_AUXEN - 0x4002 4058)
Description
When 1, the Second value is not compared for the alarm.
When 1, the Minutes value is not compared for the alarm.
When 1, the Day of Month value is not compared for the alarm.
When 1, the Day of Week value is not compared for the alarm.
When 1, the Day of Year value is not compared for the alarm.
When 1, the Month value is not compared for the alarm.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An
interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the
RTC interrupt is enabled in the NVIC.
Write: writing a 1 to this bit clears the flag.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When 0: the RTC Oscillator Fail detect interrupt is disabled.
When 1: the RTC Oscillator Fail detect interrupt is enabled. See
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The RTC Auxiliary Control register contains added interrupt flags for functions that are not
part of the Real Time Clock itself (the part recording the passage of time and generating
other time related functions). On the LPC17xx, the only added interrupt flag is for failure of
the RTC oscillator.
The RTC Auxiliary Enable Register controls whether additional interrupt sources
represented in the RTC Auxiliary control register are enabled.
All information provided in this document is subject to legal disclaimers.
Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers
Rev. 2 — 19 August 2010
Section
27.6.2.5.
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
value
NA
1
NA
Reset
value
NA
0
NA
Reset
value
0
0
0
0
0
0
0
0
NA