LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 301

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 271: UARTn Receiver Buffer Register (U0RBR - address 0x4000 C000, U2RBR - 0x4009 8000, U3RBR -
Table 272: UARTn Transmit Holding Register (U0THR - address 0x4000 C000, U2THR - 0x4009 8000, U3THR -
UM10360
User manual
Bit
7:0
31:8 -
Bit
7:0
31:8 -
Symbol
RBR
Symbol
THR
04009 C000 when DLAB = 0) bit description
0x4009 C000 when DLAB = 0) bit description
14.4.1 UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR -
14.4.2 UARTn Transmit Holding Register (U0THR - 0x4000 C000, U2THR -
14.4.3 UARTn Divisor Latch LSB register (U0DLL - 0x4000 C000, U2DLL -
Description
The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx
FIFO.
Reserved, the value read from a reserved bit is not defined.
Description
Writing to the UARTn Transmit Holding Register causes the data to be stored in the
UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and
the transmitter is available.
Reserved, user software should not write ones to reserved bits.
0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0)
The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the UnRBR.
The UnRBR is always read-only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U0LSR
register, and then to read a byte from the UnRBR.
0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0)
The UnTHR is the top byte of the UARTn TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in UnLCR must be zero in order to access the
UnTHR. The UnTHR is always write-only.
0x4009 8000, U3DLL - 0x4009 C000 when DLAB = 1) and UARTn
Divisor Latch MSB register (U0DLM - 0x4000 C004, U2DLL -
0x4009 8004, U3DLL - 0x4009 C004 when DLAB = 1)
The UARTn Divisor Latch is part of the UARTn Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce
the baud rate clock, which must be 16× the desired baud rate. The UnDLL and UnDLM
registers together form a 16-bit divisor where UnDLL contains the lower 8 bits of the
divisor and UnDLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like
a 0x0001 value as division by zero is not allowed. The Divisor Latch Access Bit (DLAB) in
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 14: LPC17xx UART0/2/3
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
Undefined
NA
Reset Value
NA
NA
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