LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 700

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
34.2.8 Bitfield instructions
Table 621
bitfields:
Table 621. Packing and unpacking instructions
Mnemonic
BFC
BFI
SBFX
SXTB
SXTH
UBFX
UXTB
UXTH
shows the instructions that operate on adjacent sets of bits in registers or
All information provided in this document is subject to legal disclaimers.
Brief description
Bit Field Clear
Bit Field Insert
Signed Bit Field Extract
Sign extend a byte
Sign extend a halfword
Unsigned Bit Field Extract
Zero extend a byte
Zero extend a halfword
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
See
Section 34.2.8.1
Section 34.2.8.1
Section 34.2.8.2
Section 34.2.8.3
Section 34.2.8.3
Section 34.2.8.2
Section 34.2.8.3
Section 34.2.8.3
UM10360
© NXP B.V. 2010. All rights reserved.
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