LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 54

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
4.7 Clock dividers
UM10360
User manual
Fig 11. PLLs and clock dividers
4.7.1 CPU Clock Configuration register (CCLKCFG - 0x400F C104)
The output of the PLL0 must be divided down for use by the CPU and the USB subsystem
(if used with PLL0, see
frequency can be determined independently from the USB subsystem, which always
requires 48 MHz with a 50% duty cycle for proper operation.
The CCLKCFG register controls the division of the PLL0 output before it is used by the
CPU. When PLL0 is bypassed, the division may be by 1. When PLL0 is running, the
output must be divided in order to bring the CPU clock frequency (CCLK) within operating
limits. An 8-bit divider allows a range of options, including slowing CPU operation to a low
rate for temporary power savings without turning off PLL0.
Note: when the USB interface is used in an application, CCLK must be at least 18 MHz in
order to support internal operations of the USB subsystem.
osc_clk
sysclk
main PLL
(PLL0...)
settings
USB PLL settings
Main PLL
USB PLL
(PLL1...)
(PLL1)
(PLL0)
All information provided in this document is subject to legal disclaimers.
(PLL0CON)
Rev. 2 — 19 August 2010
Section
CPU PLL
select
pllclk
4.6). Separate dividers are provided such that the CPU
CPU clock divider setting
USB clock divider setting
USBCLKCFG[3:0]
Chapter 4: LPC17xx Clocking and power control
CCLKCFG[7:0]
Divider
Divider
Clock
Clock
USB
CPU
USB PLL select
(PLL1CON)
usb_clk
cclk
UM10360
© NXP B.V. 2010. All rights reserved.
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